#
# OPTION COMMAND FILE created byCadence Quantus Extraction Version 22.1.1-p041 from CCL
#
capacitance \
	 -decoupling_factor 1.0 \
	 -ground_net "VSS"
distributed_processing \
	 -multi_cpu 2
extract \
	 -selection "all" \
	 -type "rc_decoupled"
extraction_setup \
	 -array_vias_spacing "auto" \
	 -max_fracture_length infinite \
	 -max_fracture_length_unit "MICRONS" \
	 -max_via_array_size \
		"auto" \
	 -net_name_space "LAYOUT"
filter_res \
	 -merge_parallel_res false \
	 -min_res 0.001
input_db -type pvs \
	 -design_cell_name "mm_osc_top layout argon" \
	 -directory_name "/home/mge41@win2k.aub.edu.lb/cadence01/runDirLVS/svdb" \
	 -format "DFII" \
	 -library_definitions_file "/home/mge41@win2k.aub.edu.lb/cadence01/cds.lib" \
	 -run_name "mm_osc_top"
log_file \
	 -file_name "/home/mge41@win2k.aub.edu.lb/cadence01/runDirLVS/svdb/qrc.mm_osc_top.log"
output_db -type extracted_view \
	 -cap_component "pcapacitor " \
	 -cap_property_name "c" \
	 -cdl_out_map_directory \
		"/home/mge41@win2k.aub.edu.lb/cadence01/runDirLVS" \
	 -device_finger_delimiter "@" \
	 -enable_cellview_check true \
	 -include_cap_model "false" \
	 -include_parasitic_cap_model "false" \
	 -include_parasitic_res_model "comment" \
	 -include_parasitic_res_width true \
	 -include_res_model "false" \
	 -res_component "presistor" \
	 -res_property_name "r" \
	 -transfer_net_expression true \
	 -view_name "typical_092525"
output_setup \
	 -directory_name "/home/mge41@win2k.aub.edu.lb/cadence01/runDirLVS/svdb" \
	 -temporary_directory_name "mm_osc_top"
process_technology \
	 -technology_corner \
		"rcx_typical" \
	 -technology_library_file "/home/pdk/gpdk045/gpdk045_v_6_0/pvtech.lib" \
	 -technology_name "gpdk045_pvs" \
	 -temperature \
		"25.0"


